Forum Discussion
anonimcs
Contributor
ContributorClock groups ignored by Timing analyzer
Hi all, I have a design with multiple clock domains. I want to ignore the timing checks for the paths where CDC happens. For this purpose, I have set clock groups in my sdc file, code can be found b...
The issue was that the .sdc file was read before all the other .ip files are read in the .qsf file. When I moved the line to read the .sdc file after reading the .ip files, the issue is gone, and I can see false paths set in the report for clock transfers. This issue was also mentioned in this article here. In case the link becomes broken in the future, I attach a screenshot of the link content below.
sstrell
Super Contributor
Super ContributorCan you show your create_clock constraints? Something is not making sense here. What is your target device and Quartus version?
anonimcsThe target device is Arria 10 and I'm using the Quartus version 21.3 Pro. I attached my .sdc file here so that you can have a better sight on my constraints.
