Forum Discussion
ContributorClock groups ignored by Timing analyzer
The issue was that the .sdc file was read before all the other .ip files are read in the .qsf file. When I moved the line to read the .sdc file after reading the .ip files, the issue is gone, and I can see false paths set in the report for clock transfers. This issue was also mentioned in this article here. In case the link becomes broken in the future, I attach a screenshot of the link content below.
New ContributorHi,
Ensure your SDC file is correctly loaded and check for typos in clock names. Verify the timing analyzer respects the constraints. You can also define false paths explicitly, like:
set_false_path -from [get_clocks { clk_25mhz_fpga }] -to [get_clocks { sg_clk }]
Generate a detailed timing report to pinpoint the issue. Make sure no incremental compilation settings are causing this problem. Lastly, check for any known issues with Quartus Pro 21.3.
Hope this helps!
anonimcsHi,
My .sdc is correctly loaded into the project and there is no typos whatsoever, I directly copy-pasted the names from the Timing Analyzer. I tried defining false paths with the syntax you suggested, but the result is the same. No ignored constraints and no applied constraints for the false paths... And yes, I still get the timing violations at the clock domain crossings.
Not sure what you meant by "a detailed timing report", these should be the details I need to look for, right ?
I applied both "Superior performance with synthesis optimizations" and "Balanced" flows, the results are the same.
Thanks for the suggestions anyways !
