Forum Discussion
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to propagate through chain and in moment when STOP occurs, propagation is sampled by registers. To do so, all it takes is to set all the bits of the first operand (input a) to ‘1’ and the bits of the second operand to ‘0’ (input b). Code which works fine for me is :
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity DelayLine is generic ( DATA_WIDTH : natural := 20 ); port ( output: out signed ((DATA_WIDTH-1) downto 0); a: in signed ((DATA_WIDTH-1) downto 0); b: in signed ((DATA_WIDTH-1) downto 0); START: in std_logic ); end DelayLine; architecture rtl of DelayLine is SIGNAL reg: signed ((DATA_WIDTH-1) downto 0); SIGNAL buf: signed ((DATA_WIDTH-1) downto 0); SIGNAL STOP: std_logic; SIGNAL I: integer := 0; begin process (START) variable s : signed ((DATA_WIDTH) downto 0); begin s := ('0' & a) + ('0' & b) + ('0' & START); buf<=s((DATA_WIDTH-1) downto 0); if (falling_edge(START)) then output<=buf((DATA_WIDTH-1) downto 0); end if; end process; end rtl; PROBLEM: Currently my only idea how to supply every adder block with two required signals ('1' and '0') is to make another two registers; one register with ones and other with zeros. Such solution is making a lots of problems in my design. My question is it possible to make some more simple circuit which will supply adders with ones and zeros. I have tried with nonsequential registers (All elements forced to high or low state) but then my carry chain gets deformation.37 Replies
Altera_Forum--- Quote Start --- Hi parasole, I am glad to see somebody with the same problem. Currently I am busy but I will contact you tomorrow, so we can discuss more about this topic ! --- Quote End --- Well, hope we will find some solutions for the problems :-) It is quite strange that so few people are interested on this area, as opposite to the ones who regularly asking why would you need to try low level design or manual placing...- Altera_Forum
So here is my progress till now. Currently I am trying to exploit fact that Quartus build adders in one column. After that with LogicLoc option I manually place delay line in wanted place. In this first phase everything works fine and I get exactly what i need. Problem starts when I move other components on chip; for some reason in some situations delay line gets deformation after changing position of some elements (Fore example I want that START block is placed at the beginning of line). Second problem is mentioned supply of cells with ones and zeros. Here is my temporary solution which is probably reason why my TDC doesn't work: I have grounded one external pin. With logic gates and and not you can make two variables ; one for state "1" and other for state "0". After that you can put this two variables to input of shift register (One shift register with ones and other with zeros). Because shift registers are fed from external pin compiler thinks that input signal can change and preserves FF's. Shift registers are driven by some random clock and that's what am I worried about because I don't know what will happen in time intervals when shift action comes up and delay line needs to be sampled. One idea is to drive shift register with really slow clock, so timing problems can be moved away.
- Altera_Forum
Got your points, I think there should be another way, however I did not find it too, at list by now.
As I stated due of this problem I turned out to low level design and after playing with LUT mask finally got it synthesized. Most interesting over here is that quartus place by default all the elements in line by using one column, at list right now without any additional components. What I found is the way Quartus feed low level, it creates automatically ground level from one cell and feed low level to all other cells. At the same time high level is feed directly, possible this is due of the fpga architecture at gates level. Any way, you may try to adapt the code for your device, not sure about the differences but assume it should not be a big deal. As a basis for my code I used another one found over here posted by FvM... - Altera_Forum
Thanks! I will investigate mentioned approach with low level primitives. Currently I am sick so my work stays at same place :(, but I will be soon back so I will contact you about progress soon!
- Altera_Forum--- Quote Start --- Thanks! I will investigate mentioned approach with low level primitives. Currently I am sick so my work stays at same place :(, but I will be soon back so I will contact you about progress soon! --- Quote End --- Sorry to hear about, hope noting serious... I am continue to play with my design and found the same as you mentioned, fitter will place the line nicelly however will mess up if adding other design entities. However logiclock solve the problem right away by assigning a region for delay line only. I left the region origin to be floating so allowing the fitter to select the best origin it think as of current design level.
- Altera_Forum
Actually, you can assign allocation for each LE®ister.
- Altera_Forum--- Quote Start --- Actually, you can assign allocation for each LE®ister. --- Quote End --- Assume it should be possible, would you point out to the right direction? BTW, any thing about your implementation?
- Altera_Forum
I was doing exactly same thing; I have placed delay line in one region with logicloc tool, but after that I have manually placed START block as close as possible to the beginning of the line. I am pretty sure that manual placement of START block in region of delay line caused mentioned problems with delay line deformation. Tomorrow I am going to do another try but just with delay line placed alone in one region. One question about your picture; what are blocks around your delay line? Also I need to ask how will You test your delay line. My current solution is usage of ALT_PLL megafunctions to create two phase shifted signals (Phase can be adjusted in range of picoseconds ). After that with simple logic I make START and STOP signal. START should be placed as close as possible to the beginning of delay line and connected to CarryIn wire. STOP signal should trigger all FF's.
- Altera_Forum
Actually as I stated, the region is only assigned to TDC line, quartus (btw 13.0sp1) alight them correctly with entry cell being the first one and correct order for every other cells.
Every thing else you may see around is second latch line and priority decoder, I did adapt the code from another TDC project I found but done for Xilinx, btw quite good source of information: http://cas.tudelft.nl/fpga_tdc/tdc_basic.html http://www.ohwr.org/projects/tdc-core/wiki For testing purpose I had similar idea but phase shift indeed is very good point, I have one ready module thus will try to use it. - Altera_Forum
If I understood correctly the way you try to measure... I think you need to perform kind of test-bench, i.e. start signal should be longer then one clock period and stop signal to be triggered only once so than you may save the result until you read it for interpretation. I would suggest to use on ff to trigger start signal by clock so let it be high until you reset it for new measurement. For stop signal probably you may use a ff and &gate which will be locked by ff. again ff reset signal would be used for next measurement. That means every measurement cycle will happen only once at every reset signal...
From my side I did not come to the point of testing, for me this is hobby thus playing only on evenings... nevertheless, I will try to build a test bench in the way I described, however in order to be able to analyze the data I think about simple serial interface for collecting TDC measurements...
