Can't resolve multiple constant drivers?

I can´t find the signal LSD_SEG in the code you posted.

But one of the rules of VHDL is that you cannot assign a signal in more than one place. This error is a result of you assigning a value to the specified signal in more than one place.

Check that you are not assigning this signal outside of a process and inside, or in two or more different processes or in two or more different places outside of a process.

Right clicking on the warning in Quartus and clicking help, should help you to understand why you get this error.

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I can´t find the signal LSD_SEG in the code you posted.

But one of the rules of VHDL is that you cannot assign a signal in more than one place. This error is a result of you assigning a value to the specified signal in more than one place.

Check that you are not assigning this signal outside of a process and inside, or in two or more different processes or in two or more different places outside of a process.

Right clicking on the warning in Quartus and clicking help, should help you to understand why you get this error.

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My bad, the signals are LSD_7SEG & MSD_7SEG. That's exactly what my problem is, im assigning a signal in more than one place. hw can i not do that and still achieve the desired results?

Thanx for quick response

Regards

Dante

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Hi,

I'm not a real VHDl expert, but as far as I know is the "'EVENT" only allowed for single bits.

'EVENT on vector is not syntheziable. Why not using a PROCESS with a sensitivity list ?

Your assign values to MSD_7SEG and LSD_7SEG in three different processes. That causes the multiple driver error. You have to combine the processes to one. Additinonal you have two wait statements in one process, which is also not allowed.

Kind regards

GPK

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At pletz, ive already changed that "event" part, thank you. I tried combining the processes. it compiles but doesnt work as it should. this code works superbly on the UP2 board. Can you show me exactly to combine the processes?

Regards

Dante

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I tried combining the processes. it compiles but doesnt work as it should.

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Sounds plausible. Combining the processes creates legal VHDl semantic, but not necessarily intended behaviour. The basic problem is, that you have to resolve the conflicting assignments logically. Whatever code you write, you have to know which of the multiple signal assignments should be in effect at different times. The design compiler will resolve the conflict only based on code placement. The last assignment wins.

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Sounds plausible. Combining the processes creates legal VHDl semantic, but not necessarily intended behaviour. The basic problem is, that you have to resolve the conflicting assignments logically. Whatever code you write, you have to know which of the multiple signal assignments should be in effect at different times. The design compiler will resolve the conflict only based on code placement. The last assignment wins.

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I even tried using a multiplexer, both parts work but the one part is not displayed. for example, when i press the push button, 7 seg displays, display the contents stored for push button event but when i release it, last key pressed on the keyboard is displayed and thats not how it should work.

This is how it should work:

1. when i press a key on the keyboard, the contents associated with that key should be displayed and stay displayed.

2. when i press the push button, the contents associated with push button counter should be displayed and stay displayed.

3. (1) and (2) work fine independently, problem arises when i put them in a single file.

im new to vhdl and like i said, i've been trying to resolve this since friday and this project is due tomorrow. please help pls. i've attached a more readable code, pls help me correct it.:confused:

Regards

Dante

Aside from multiple drivers, a huge problem you're going to have is your clocking scheme.

You have generated your own clock using logic, and you are clocking other processes with that logic generated clock. In FPGAs, this is a big problem as it can cause all sorts of timing issues. Its much better to generate an enable for registers that are clocked from the source clock.

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Aside from multiple drivers, a huge problem you're going to have is your clocking scheme.

You have generated your own clock using logic, and you are clocking other processes with that logic generated clock. In FPGAs, this is a big problem as it can cause all sorts of timing issues. Its much better to generate an enable for registers that are clocked from the source clock.

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Hi tricky, can you pls help with some form of example? the cyclone II DE1 board didnt have any timing issues so i didnt think that would be a problem. The clock that ive generated is only used by the push button process (i think), coz the keyboard has clock conneted to it already.

I been with vhdl for 2 weeks now, so everything is just new to me. :(