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Aside from multiple drivers, a huge problem you're going to have is your clocking scheme.
You have generated your own clock using logic, and you are clocking other processes with that logic generated clock. In FPGAs, this is a big problem as it can cause all sorts of timing issues. Its much better to generate an enable for registers that are clocked from the source clock.
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Hi tricky, can you pls help with some form of example? the cyclone II DE1 board didnt have any timing issues so i didnt think that would be a problem. The clock that ive generated is only used by the push button process (i think), coz the keyboard has clock conneted to it already.
I been with vhdl for 2 weeks now, so everything is just new to me. :(
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