Can't resolve multiple constant drivers?

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I tried combining the processes. it compiles but doesnt work as it should.

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Sounds plausible. Combining the processes creates legal VHDl semantic, but not necessarily intended behaviour. The basic problem is, that you have to resolve the conflicting assignments logically. Whatever code you write, you have to know which of the multiple signal assignments should be in effect at different times. The design compiler will resolve the conflict only based on code placement. The last assignment wins.