Forum Discussion

Altera_Forum

Honored Contributor

9 years ago

Bug report: Quartus will not load correct library in VHDL

Hello, I am a software-engineer and try to design circuits as a hobby.

I had wanted to hide some modules/entities, such as C++'s namespace, or C's file-scope,

so I have written designs in Altera-extended-VHDL, and got a bug.

I have written the codes as below;

lib.vhd:


-- synthesis library my_lib
library ieee, arithmetic;
use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
entity calc is
    port (
        x: in std_logic_vector(63 downto 0);
        y: in std_logic_vector(63 downto 0);
        z: out std_logic_vector(63 downto 0)
    );
end;
architecture calc of calc is
begin
    z <= x + y;
end;
-- synthesis library my_lib2
library ieee, arithmetic;
use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
entity calc is
    port (
        x: in std_logic_vector(63 downto 0);
        y: in std_logic_vector(63 downto 0);
        z: out std_logic_vector(63 downto 0)
    );
end;
architecture calc of calc is
    signal b: std_logic_vector(127 downto 0);
begin
    b <= x * y;
    z <= b(63 downto 0);
end;

main.vhd:


library ieee, arithmetic;
use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
entity delay is
    generic (
        L : integer
    );
    port (
        clock : in std_logic;
        x : in std_logic_vector(L - 1 downto 0);
        y : out std_logic_vector(L - 1 downto 0)
    );
end;
architecture delay of delay is
    signal d : std_logic_vector(L - 1 downto 0);
begin
    process (clock)
    begin
        if clock 'event and clock = '1' then
            d <= x;
        end if;
    end process;
    y <= d;
end;
library ieee, arithmetic;
use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
library my_lib;
use my_lib.all;
use work.all;
entity main is
    port (
        CLOCK_125_p : in std_logic;
        LEDG : out std_logic_vector(7 downto 0)
    );
end;
architecture main of main is
    constant L: integer := 64;
    signal c: std_logic_vector(L - 1 downto 0)
        := (
            0 => '1',
            1 => '1',
            others => '0'
        );
    signal d: std_logic_vector(L - 1 downto 0);
begin
    i0: calc
        port map(c, c, d);
    
    i1: delay
        generic map(L => L)
        port map(CLOCK_125_p, d, c);
    
    process (CLOCK_125_p) is
    begin
        if CLOCK_125_p 'event and CLOCK_125_p = '1' then
            LEDG(7 downto 0) <= d(L - 1 downto L - 8);
        end if;
    end process;
end;

And compile... Ok, it looks additive module is loaded.

Then, edit only the main.vhd s/my_lib/my_lib2/, and re-compile...

Ok? Let us see.

Expected: my_lib2's "calc" instantiated, RTL Viewer says calc:i0 contains multiplicative module, and some DSP-blocks are used for the multiplication, and so on.

Occurred: it looks my_lib's "calc" instantiated, RTL Viewer says calc:i0 still contains additive module, and no DSP-blocks are used, and so on.

How to fix: Clean-up the project to Menu -> Project -> Clean Project..., then re-compile.

Could you please re-produce this problem?

Thank you for reading.

Environments Info:

Windows 7 Ultimate Service Pack 1

Intel(R) Core(TM) i7-5820K CPU @ 3.30GHz

Memory: 64GiB, using about 32GiB

Quartus Prime Version 16.0.2 Build 222 07/20/2016 SJ Lite Edition

Cyclone V GX Starter Kit (5CGXFC5C6F27C7)

11 Replies

Altera_Forum
Honored Contributor
9 years ago
First of all - altera dont really monitor this forum. To raise a bug ticket you need to log into mysupport on the altera website.

What is this altera-extended-vhdl you speak of? there is no such thing.
VHDL has no ability to "hide" modules behind namespaces.
VHDL has libraries. Also, quartus doesnt necessarily follow all the library rules in VHDL, unless you are explicit about it in the compile options, either in the file settings or with the -library switch in the .qsf file. Otherwise it just dumps everything into the work library and pretty much ignores any library names in your code. This is probably the root of your problem, as it will just search through the library for the first entity called "calc", even though you think you've put them into two different libraries.

I also note in your main.vhd, unless you've compiled a calc component into the arithmetic.std_logic_arith package (why have you made your own version of a non-standard VHDL package?), there will be an in the compiler that calc doesnt exist. Where is the code for your std_logic_arith package? Why are you doing arithmatic with std_logic_vectors? they are not meant to represent numbers, they are just a collection of bits. They could be integers, signed, unsigned, floats, fixed point - you just have no way of knowing. Why not use the numeric_std package (which part of the VHDL standard) that allows you to do arithmatic on signed and unsigned at the same time in the same file.

Either way, you're coming at compilation like a programmer with complicated name spaces. These just dont exist in VHDL or quartus.
Altera_Forum
Honored Contributor
9 years ago
Thank you for reply.

> First of all ...
Ok, I am going to send the report to it. Thank you coach me.

> What is this altera-extended-vhdl you speak of? there is no such thing.
I had not read the 2008 spec because it has to purchase, so I had read the 1987's.
I have thought that the synthesis-directive is not part of the IEEE's VHDL.
In any case, Altera has implemented the directive.
http://quartushelp.altera.com/current/#hdl/vhdl/vhdl_file_dir.htm

--- Quote Start ---
The Quartus® Prime software supports the following VHDL synthesis attributes and synthesis directives, which you can use in a VHDL Design File (.vhd) Definition to direct Analysis & Synthesis to perform or not perform certain actions when synthesizing a design:
...
library: A VHDL synthesis directive that sets the destination library for the design units in a VHDL Design File.
--- Quote End ---

Altera-extended-vhdl that I said means VHDL with the synthesis directive function.

> VHDL has no ability to "hide" modules behind namespaces.
it will be incorrect partially.
In at least Altera-implemented-version, VHDL has ability to port modules into namespaces (libraries),
that hides sub-modules (if does not write "use xxx.all;"), that I just had wanted function.

> I also note in your main.vhd, ...
Thank you for teach me the numeric_std and so on. I had not known their.
But it works that I have posted in my environment (let us try it), in spite of I do not know why it works nor how.

Thanks.
Altera_Forum
Honored Contributor
9 years ago
Is the --synthesis library directive per file or per module?
Altera_Forum
Honored Contributor
9 years ago
Synthesis directives are not part of VHDL, they are just attributes that altera specify to affect the behaviour of their synthesisor. It is not extension to VHDL - anyone can define their own attributes in VHDL.

--- Quote Start ---

> VHDL has no ability to "hide" modules behind namespaces.
it will be incorrect partially.
In at least Altera-implemented-version, VHDL has ability to port modules into namespaces (libraries),
that hides sub-modules (if does not write "use xxx.all;"), that I just had wanted function.

--- Quote End ---

Like I said, unless you specify the libraries in the libraries settings or in the .qsf file, quartus will ignore any user libraries (or namespaces as you like to call them) and just throw everything in the work library.
If you post your whole code and project, maybe it will be clearer what you're doing..
Altera_Forum
Honored Contributor
9 years ago
Thank you replies.

> Is the --synthesis library directive per file or per module?
I have used the directive per module.

> Synthesis directives are not part of VHDL,...
I have thought that the directives should part of VHDL (like C), and not defined the synthesis directives in the IEEE's.

I have zipped the project and uploaded to the dropbox.
https://www.dropbox.com/s/q59tmjjrjj70img/vhdlproject.zip?dl=0
First Step, open the unzipped project, and compile (Ctrl+L).
Second, modify main.vhd s/my_lib/my_lib2/ at line 29, 30, and save (Ctrl+S).
Finally, re-compile (Ctrl+L).
Then, open it in RTL-Viewer, open calc:i0 node, you will see it contains additive module.
But mylib2::calc (in lib.vhd) uses multiply...
Next Step, Menu -> Project -> Clean Project... to clean-up the project, then, re-compile (Ctrl+L).
Now you will see calc:i0 contains a multiplicative module in RTL-Viewer.
Altera_Forum
Honored Contributor
9 years ago
if you remove reference to work.all, do you still get the same problem?
I still feel this is a problem with the code. You dont have a component declaration for calc, so the compiler should have no knowledge of calc - if you try and compile this code in modelsim (which is a much stricter VHDL compiler) then once you fix the missing std_logic_1164 library, you get the following error:

# ** Error (suppressible): main.vhd(52): (vcom-1141) Identifier "calc" does not identify a component declaration. # # -- Loading entity delay # ** Error (suppressible): main.vhd(55): (vcom-1141) Identifier "delay" does not identify a component declaration.

Because there are no components, it doesnt know what the calc or delay entities look like. You have two options for this:
1. Use a component in the main.vhd.

Doing this allows the compiler to see what the component looks like as a black box, and compile your instantitiation against the black box. Once compilation is finished, the mapper maps the instantiation to an entity within the same library.

2. use direct instantitation:

i0: entity my_lib.calc port map (

So what I suspect is happening is Quartus is being it's usual lax self when it comes to libraries, and because you didnt specify a component or use direct instantiation, Quartus is pulling the first version of calc it finds in ANY library.

Secondly - on synthesis directives - you'll find that all synthesis directives are embedded in comments when they're not attributes. So there is no way they could be part of the VHDL standard. They are switches Quartus understands. Xilinx (and other synth engines) offer similar understanding, so they are a defacto standard, but not an official standard.

Altera_Forum

Honored Contributor

9 years ago

> if you remove reference to work.all, do you still get the same problem?

Yes, I have tried to write the components (1) and direct instantiation (2),

and now they are modelsim-compatible codes,

it still get the same problem.

main.vhd are now blow script:


library ieee;
use ieee.numeric_std.all;
entity delay is
	generic (
		L : integer
	);
	port (
		clock : in bit;
		x : in unsigned(L - 1 downto 0);
		y : out unsigned(L - 1 downto 0)
	);
end;
architecture delay of delay is
	signal d : unsigned(L - 1 downto 0);
begin
	process (clock)
	begin
		if clock 'event and clock = '1' then
			d <= x;
		end if;
	end process;
	y <= d;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library my_lib;
use my_lib.all;
entity main is
	port (
		CLOCK_125_p : in bit;
		LEDG : out unsigned(7 downto 0)
	);
end;
architecture main of main is
	constant L: integer := 64;
	signal c: unsigned(L - 1 downto 0)
		:= (
			0 => '1',
			1 => '1',
			others => '0'
		);
	signal d: unsigned(L - 1 downto 0);
	
	component delay
		generic (
			L : integer
		);
		port (
			clock : in bit;
			x : in unsigned(L - 1 downto 0);
			y : out unsigned(L - 1 downto 0)
		);
	end component;
	
	component calc
		port (
			x: in unsigned(63 downto 0);
			y: in unsigned(63 downto 0);
			z: out unsigned(63 downto 0)
		);
	end component;
	
begin
	i0: entity my_lib.calc
		port map(c, c, d);
	
	i1: delay
		generic map(L => L)
		port map(CLOCK_125_p, d, c);
	
	process (CLOCK_125_p) is
	begin
		if CLOCK_125_p 'event and CLOCK_125_p = '1' then
			LEDG(7 downto 0) <= d(L - 1 downto L - 8);
		end if;
	end process;
end;

What are still wrong?

Note:

I did not validate design by ModelSim, but just by RTL-Viewer because this circuit is sufficiently small.

Environment Info:

ModelSim ALTERA STARTER EDITION 10.4d Revision: 2015.12

Altera_Forum
Honored Contributor
9 years ago
Why not just make your life easier and call them :
calc_mult
calc_add

That way you can have adders and multipliers in the same file.

Hiding entities behind libraries is not standard practice in VHDL. it is usual to describe entities by what they actually do.
Altera_Forum
Honored Contributor
9 years ago
> Why not just make your life easier and call them :
Because
(1) it is a minimum-sample.
In my real project, they will be called such as "local_xxx" or "sub_xxx",
that will be conflicts someday and hand-mangling makes hard to read/write codes, and
(2) for the polymorphism. To implements and evaluate new ideas, algorithms and/or logics for the FPGA,
to change the sub-module implemented on logic X to logic Y's,
it is one of a simple way to change the library.

To achieve (2) will easy; Select the architecture or use macros to replace, but (1) -- hiding modules is a best way to avoid conflicts -- is difficult.
Altera_Forum
Honored Contributor
9 years ago
VHDL does not support polymorphism (in a programming sense).

For now, the easiest way to work around is just have different names for the entities - calc1, calc2. That way you know for sure whats going to happen.= - its how real projects work. When you're compiling for an FPGA, you need to know the architecture when you compile, and it cannot change while it's running - it needs a recompile each time.

Or you could just have 2 projects - one for 1 set, and one for the other.

And then you're going to run into problems when you use modelsim, because it doesnt understand the --synthesis pragmas (because they are not relevent to it).

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