Bug report: Quartus will not load correct library in VHDL

VHDL does not support polymorphism (in a programming sense).

For now, the easiest way to work around is just have different names for the entities - calc1, calc2. That way you know for sure whats going to happen.= - its how real projects work. When you're compiling for an FPGA, you need to know the architecture when you compile, and it cannot change while it's running - it needs a recompile each time.

Or you could just have 2 projects - one for 1 set, and one for the other.

And then you're going to run into problems when you use modelsim, because it doesnt understand the --synthesis pragmas (because they are not relevent to it).