Honored Contributor
Honored Contributor> if you remove reference to work.all, do you still get the same problem?
Yes, I have tried to write the components (1) and direct instantiation (2), and now they are modelsim-compatible codes, it still get the same problem. main.vhd are now blow script:
library ieee;
use ieee.numeric_std.all;
entity delay is
generic (
L : integer
);
port (
clock : in bit;
x : in unsigned(L - 1 downto 0);
y : out unsigned(L - 1 downto 0)
);
end;
architecture delay of delay is
signal d : unsigned(L - 1 downto 0);
begin
process (clock)
begin
if clock 'event and clock = '1' then
d <= x;
end if;
end process;
y <= d;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library my_lib;
use my_lib.all;
entity main is
port (
CLOCK_125_p : in bit;
LEDG : out unsigned(7 downto 0)
);
end;
architecture main of main is
constant L: integer := 64;
signal c: unsigned(L - 1 downto 0)
:= (
0 => '1',
1 => '1',
others => '0'
);
signal d: unsigned(L - 1 downto 0);
component delay
generic (
L : integer
);
port (
clock : in bit;
x : in unsigned(L - 1 downto 0);
y : out unsigned(L - 1 downto 0)
);
end component;
component calc
port (
x: in unsigned(63 downto 0);
y: in unsigned(63 downto 0);
z: out unsigned(63 downto 0)
);
end component;
begin
i0: entity my_lib.calc
port map(c, c, d);
i1: delay
generic map(L => L)
port map(CLOCK_125_p, d, c);
process (CLOCK_125_p) is
begin
if CLOCK_125_p 'event and CLOCK_125_p = '1' then
LEDG(7 downto 0) <= d(L - 1 downto L - 8);
end if;
end process;
end;
