Bug report: Quartus will not load correct library in VHDL

if you remove reference to work.all, do you still get the same problem?

I still feel this is a problem with the code. You dont have a component declaration for calc, so the compiler should have no knowledge of calc - if you try and compile this code in modelsim (which is a much stricter VHDL compiler) then once you fix the missing std_logic_1164 library, you get the following error:

#  ** Error (suppressible): main.vhd(52): (vcom-1141) Identifier "calc" does not identify a component declaration.
#  
#  -- Loading entity delay
#  ** Error (suppressible): main.vhd(55): (vcom-1141) Identifier "delay" does not identify a component declaration.

Because there are no components, it doesnt know what the calc or delay entities look like. You have two options for this:

1. Use a component in the main.vhd.

Doing this allows the compiler to see what the component looks like as a black box, and compile your instantitiation against the black box. Once compilation is finished, the mapper maps the instantiation to an entity within the same library.

2. use direct instantitation:

i0: entity my_lib.calc
port map ( 

So what I suspect is happening is Quartus is being it's usual lax self when it comes to libraries, and because you didnt specify a component or use direct instantiation, Quartus is pulling the first version of calc it finds in ANY library.

Secondly - on synthesis directives - you'll find that all synthesis directives are embedded in comments when they're not attributes. So there is no way they could be part of the VHDL standard. They are switches Quartus understands. Xilinx (and other synth engines) offer similar understanding, so they are a defacto standard, but not an official standard.