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EGrub
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7 years ago

BUG in simulation library for dcfifo_mixed_widths with Modelsim

If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails.

With the read request signal the output changes immediately (without one clock of output delay).

See images with same clock and with different clock!

I wired everything into a struct but the signals are wires!

Different clock is fine, output is one clock later.

Using the same clock, you can see that the output changes immediately!

I have recognized the issue in Quartus 13.1, 15.1 and 17.1.

@ Intel:

Please answer as soon as possible with your suggestions!

BR

Erich

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