Forum Discussion
BUG in simulation library for dcfifo_mixed_widths with Modelsim
If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails.
With the read request signal the output changes immediately (without one clock of output delay).
See images with same clock and with different clock!
I wired everything into a struct but the signals are wires!
Different clock is fine, output is one clock later.
Using the same clock, you can see that the output changes immediately!
I have recognized the issue in Quartus 13.1, 15.1 and 17.1.
@ Intel:
Please answer as soon as possible with your suggestions!
BR
Erich
30 Replies
- AndyN
Occasional Contributor
Do you have the intended_device_family parameter set to something other than default? For some reason, the simulation models for the fifos seem to do strange things otherwise...
Hope that helps,
Andy
- EGrub
Occasional Contributor
Hi Andy!
Thank you for your reply. I've set it to:
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
I don't think that is the problem for the simulation, I think the issue is in the simulation lib altera_mf.v and dcfifo_sync
There they set the flag i_showahead_flag2 with the wr and the rd clock
and the output does not depend on clock but on posedge i_showahead_flag2:
always @(posedge i_showahead_flag)
begin
i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
i_showahead_flag2 <= 1'b0;
end // @(posedge i_showahead_flag)
and at the end:
assign q = i_q_tmp;
So I think that is the issue
Regards,
Erich
- EGrub
Occasional Contributor
My workaround was to delay Wr and Rd signal by a few ps but the behavior of the lib is wrong!
Please Intel test it and fix the bug!
Regards,
Erich
- KhaiChein_Y_Intel
Regular Contributor
Hi EGrub,
Could you provide the design for investigation? Which version of the software you are using?
Thanks
- EGrub
Occasional Contributor
Hi YY!
As I have written in my first post: I have recognized the issue in Quartus 13.1, 15.1 and 17.1.
To provide you with something, how is the procedure now with NDAs? Is the old NDA with Altera still valid? How to send you the files? I will for sure not upload it to the forum.
But it should be easy to test for you by instantiating a dual clock fifo with different bitwidths and lookahead. Additional information on timings you can extract from my screenshots.
Regards,
Erich
- KhaiChein_Y_Intel
Regular Contributor
Hi,
It would be helpful if you can provide design that is non-confidential for investigation.
Thanks.
- EGrub
Occasional Contributor
Hi YY!
In advance sorry for the following reply, it is nothing against you personally and I know it would maybe fit better into the flames, but:
Intel decided to replace a good working support tool (the old service requests) by a non working forum at all with the following drawbacks:
- No direct support
- The forum has a lot of bugs it self!!!
- No subcategories
- no possibility to provide confidential data
- the old forum worked better
- and some more
So no I will not provide you with my simulation because you will not be able to run it anyway.
No I will not provide you with a non-confidential design because I will not get time from my boss to generate it.
Please report to your boss that I'm unhappy with the overall support (not your support) but the type of support and the forum it self.
Regards,
Erich
- KhaiChein_Y_Intel
Regular Contributor
Hi,
We shall communicate using private message.
Thanks
- Kay
New Contributor
Are you running gate level simulation or RTL simulation?
- EGrub
Occasional Contributor
Hi Kay!
I do RTL simulation.
Regards,
Erich