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EGrub
Occasional Contributor
Occasional ContributorBUG in simulation library for dcfifo_mixed_widths with Modelsim
If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails. With the read request signal the output changes immedia...
EGrubOccasional Contributor
Occasional ContributorHi YY!
As I have written in my first post: I have recognized the issue in Quartus 13.1, 15.1 and 17.1.
To provide you with something, how is the procedure now with NDAs? Is the old NDA with Altera still valid? How to send you the files? I will for sure not upload it to the forum.
But it should be easy to test for you by instantiating a dual clock fifo with different bitwidths and lookahead. Additional information on timings you can extract from my screenshots.
Regards,
Erich
