BUG in simulation library for dcfifo_mixed_widths with Modelsim

Hi Andy!

Thank you for your reply. I've set it to:

dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",

I don't think that is the problem for the simulation, I think the issue is in the simulation lib altera_mf.v and dcfifo_sync

There they set the flag i_showahead_flag2 with the wr and the rd clock

and the output does not depend on clock but on posedge i_showahead_flag2:

always @(posedge i_showahead_flag)

begin

i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];

i_showahead_flag2 <= 1'b0;

end // @(posedge i_showahead_flag)

and at the end:

assign q = i_q_tmp;

So I think that is the issue

Regards,

Erich