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EGrub
Occasional Contributor
Occasional ContributorBUG in simulation library for dcfifo_mixed_widths with Modelsim
If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails. With the read request signal the output changes immedia...
EGrubOccasional Contributor
Occasional ContributorMy workaround was to delay Wr and Rd signal by a few ps but the behavior of the lib is wrong!
Please Intel test it and fix the bug!
Regards,
Erich
