Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Best way to code flop w/asynch reset?

Hi - I've lots of experience in Verilog, but am learning VHDL.

Question: Is this...

process(clk,rst_l) begin

if rst_l = '0' then

sig <= '0';

elsif rising_edge(clk) then

sig <= expression;

end if;

end process;

the best way to do the equivalent of

always @(posedge clk or negedge rst_l) begin

if (!rst_l) sig <= 0;

else begin

sig <= expression;

end

end

(i.e., flop with asynch reset)

I'm asking because in Verilog it's sort of by convention that if you do it -just that way- then all the synthesizers infer you want an asynch flop and the else expression is clocked. I want to make sure I'm doing it the most general way (i.e., least likely for a synth to mis-interpret) for VHDL.

THANKS!

/j

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hey - thanks rbugalho - I try to research these myself but if I have any other hard ones I'll post

    best!

    /j
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Two additional remarks.

    - You can browse the VHDL templates in the Quartus editor to learn about common language constructs.

    - There's a specification IEEE 1076.6 ieee standard for vhdl register transfer level (rtl) synthesis trying to define a VHDL subset that should be understood by all synthesis tools. Although Quartus is not 100% following this (newer) standard, it almost applies to Quartus synthesis.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    If I have questions about what VHDL synthesizes to, I use the Quartus RTL viewer and look at what the code synthesizes to :)

    Tools->Netlist Viewers->RTL Viewer

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    last time I looked, Quartus synthesizes everything to ALM/LUTs - not as easy to read as an ASIC gate-level netlist 8-}

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    last time I looked, Quartus synthesizes everything to ALM/LUTs - not as easy to read as an ASIC gate-level netlist 8-}

    --- Quote End ---

    But for things like asynchronous reset, synchronous reset, enable, clock enable, etc., its very useful for seeing whether the VHDL codes to a single signal that connects to a register port, or whether a mux is created in front of the register.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    last time I looked, Quartus synthesizes everything to ALM/LUTs - not as easy to read as an ASIC gate-level netlist 8-}

    --- Quote End ---

    The RTL viewer doesn't show ALM/LUTs; it shows the design using logic blocks, big (ie, multiplexers, adders, etc) and small (ANDs, ORs, etc).

    It's a great view to understand how the synthesis tool is interpreting your HDL.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    hm - well to be honest I haven't tried it in a long time

    thanks!

    /j
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    It's a great view to understand how the synthesis tool is interpreting your HDL.

    --- Quote End ---

    The first thing I do after a Analysis ans Synthesis is inspecting the RTL-diagram!

    I tend to divide my design in such a way that I get (if possible) small RTL-diagrams with only blocks, and only at the lowest level the logic will become visible. I even code a state machine in its own .vhd file so I can see what the data-flow is, without the state-machine logic cluttering the diagram. So I developed sub-modules for almost every task like counting up or down, multiplexing std_logic_vectors, priority encoders, etc., anything as long as it helps simpliying the RTL-diagram to an easy-to-follow collection of connected blocks.