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It's a great view to understand how the synthesis tool is interpreting your HDL.
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The first thing I do after a Analysis ans Synthesis is inspecting the RTL-diagram!
I tend to divide my design in such a way that I get (if possible) small RTL-diagrams with only blocks, and only at the lowest level the logic will become visible. I even code a state machine in its own .vhd file so I can see what the data-flow is, without the state-machine logic cluttering the diagram. So I developed sub-modules for almost every task like counting up or down, multiplexing std_logic_vectors, priority encoders, etc., anything as long as it helps simpliying the RTL-diagram to an easy-to-follow collection of connected blocks.
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