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Altera_Forum's avatar
Altera_Forum
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14 years ago

Best way to code flop w/asynch reset?

Hi - I've lots of experience in Verilog, but am learning VHDL. Question: Is this... process(clk,rst_l) begin if rst_l = '0' then sig <= '0'; elsif rising_e...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

last time I looked, Quartus synthesizes everything to ALM/LUTs - not as easy to read as an ASIC gate-level netlist 8-}