Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Best way to code flop w/asynch reset?

Hi - I've lots of experience in Verilog, but am learning VHDL. Question: Is this... process(clk,rst_l) begin if rst_l = '0' then sig <= '0'; elsif rising_e...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If I have questions about what VHDL synthesizes to, I use the Quartus RTL viewer and look at what the code synthesizes to :)

Tools->Netlist Viewers->RTL Viewer

Cheers,

Dave