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Altera_Forum
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14 years ago

Best way to code flop w/asynch reset?

Hi - I've lots of experience in Verilog, but am learning VHDL. Question: Is this... process(clk,rst_l) begin if rst_l = '0' then sig <= '0'; elsif rising_e...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Two additional remarks.

- You can browse the VHDL templates in the Quartus editor to learn about common language constructs.

- There's a specification IEEE 1076.6 ieee standard for vhdl register transfer level (rtl) synthesis trying to define a VHDL subset that should be understood by all synthesis tools. Although Quartus is not 100% following this (newer) standard, it almost applies to Quartus synthesis.