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Altera_Forum's avatar
Altera_Forum
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14 years ago

Best way to code flop w/asynch reset?

Hi - I've lots of experience in Verilog, but am learning VHDL. Question: Is this... process(clk,rst_l) begin if rst_l = '0' then sig <= '0'; elsif rising_e...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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last time I looked, Quartus synthesizes everything to ALM/LUTs - not as easy to read as an ASIC gate-level netlist 8-}

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The RTL viewer doesn't show ALM/LUTs; it shows the design using logic blocks, big (ie, multiplexers, adders, etc) and small (ANDs, ORs, etc).

It's a great view to understand how the synthesis tool is interpreting your HDL.