Honored ContributorHi,
I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with:create_clock -name "clk" -period 5.000ns create_clock -name "clock2" -period 40.000ns 
Honored ContributorYou need to use 'create_generated_clock'.
See quartus help on create_generated_clock (http://quartushelp.altera.com/15.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_create_generated_clock.htm). Cheers, AlexHonored Contributorcreate_generated_clock -source [get_ports {clk}] <relationship to source> <target>
What structure in your design is creating clock2? If it's a PLL, you can use derive_pll_clocks to automatically create the generated clock. If not, you have to use create_generated_clock.Honored ContributorThank you both but I still have another warning:
Warning (332060): Node: *|clock2 was determined to be a clock but was found without an associated clock assignment.
Warning (332061): Virtual clock clock2 is never referenced in any input or output delay assignment.
Hi,
--- Quote Start --- Warning (332060): Node: *|clock2 was determined to be a clock but was found without an associated clock assignment. --- Quote End --- Is related to the timing constrains not satisfied. --- Quote Start --- Warning (332061): Virtual clock clock2 is never referenced in any input or output delay assignment. --- Quote End --- Check that the virtual clock is not originally intended as non-virtual clock and specify the clock targets. Already addressed in previous thread. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)Honored ContributorA virtual clock is created if you use create_clock and then don't set a target (an input clock port). It's used with set_input_delay or set_output_delay as the reference clock that drives the "upstream" or "downstream" device to/from the FPGA.
Post your updated sdc code.Honored ContributorThank you both.
Please tell me exactly what I have to do. Here is my sdc code:#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
#
# ************************************************************
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name "clk" -period 5.000ns
create_generated_clock -divide_by 8 -name clock2 -source
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
The two warnings (note they are not errors) are directly related. You're creating a virtual clock but then not referencing it with any input or output port delay setting - set_input_delay or set_output_delay as sstrell suggested.
Please note: it does not mean the timing constraint has not been satisfied, as suggested elsewhere in the thread. Post your updated constraints. Cheers, AlexHonored ContributorMy sdc constraints are waiting for a moderator to agree...
Honored ContributorHonored ContributorYou have not specified a target for your create_generated_clock constraint. That's why it's coming up as a virtual clock. If you are using a PLL, the target should be the output clock pin (get_pins) of the PLL, or just use derive_pll_clocks as mentioned.
