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Honored Contributor
Honored Contributorassign two clocks
Hi, I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with: create_clock -name "clk" -period 5.000ns but my second clock (named "clock2")...
Altera_ForumHonored Contributor
Honored ContributorHi,
--- Quote Start --- Warning (332060): Node: *|clock2 was determined to be a clock but was found without an associated clock assignment. --- Quote End --- Is related to the timing constrains not satisfied. --- Quote Start --- Warning (332061): Virtual clock clock2 is never referenced in any input or output delay assignment. --- Quote End --- Check that the virtual clock is not originally intended as non-virtual clock and specify the clock targets. Already addressed in previous thread. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
