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Honored Contributor
Honored Contributorassign two clocks
Hi, I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with: create_clock -name "clk" -period 5.000ns but my second clock (named "clock2")...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- create_generated_clock -source [get_ports {clk}] <relationship to source> <target> What structure in your design is creating clock2? If it's a PLL, you can use derive_pll_clocks to automatically create the generated clock. If not, you have to use create_generated_clock. --- Quote End --- You need to answer this question before people can really help you. PLL? Did you try "derive_pll_clocks"? If the answer is yes to both these questions then you don't need the sdc constraints t for clock 2 at all (it is generated by "derive_pll_clocks") Obviously you don't have a 200MHz and 25MHz clock coming directly from the same clock pin?
