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Altera_Forum's avatar
Altera_Forum
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8 years ago

assign two clocks

Hi, I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with: create_clock -name "clk" -period 5.000ns but my second clock (named "clock2")...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The two warnings (note they are not errors) are directly related. You're creating a virtual clock but then not referencing it with any input or output port delay setting - set_input_delay or set_output_delay as sstrell suggested.

Please note: it does not mean the timing constraint has not been satisfied, as suggested elsewhere in the thread.

Post your updated constraints.

Cheers,

Alex