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Honored Contributor
Honored Contributorassign two clocks
Hi, I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with: create_clock -name "clk" -period 5.000ns but my second clock (named "clock2")...
Altera_ForumHonored Contributor
Honored ContributorA virtual clock is created if you use create_clock and then don't set a target (an input clock port). It's used with set_input_delay or set_output_delay as the reference clock that drives the "upstream" or "downstream" device to/from the FPGA.
Post your updated sdc code.
