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Altera_Forum's avatar
Altera_Forum
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8 years ago

assign two clocks

Hi, I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with: create_clock -name "clk" -period 5.000ns but my second clock (named "clock2")...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

You have not specified a target for your create_generated_clock constraint. That's why it's coming up as a virtual clock. If you are using a PLL, the target should be the output clock pin (get_pins) of the PLL, or just use derive_pll_clocks as mentioned.