Forum Discussion
Altera_Forum
Honored Contributor
8 years agoassign two clocks
Hi, I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with: create_clock -name "clk" -period 5.000ns but my second clock (named "clock2")...
Altera_Forum
Honored Contributor
8 years agoThank you both.
Please tell me exactly what I have to do. Here is my sdc code:#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
#
# ************************************************************
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name "clk" -period 5.000ns
create_generated_clock -divide_by 8 -name clock2 -source
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints