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Altera_Forum's avatar
Altera_Forum
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10 years ago

Altera PCIe Hard IP avmm for cyclone V quartus synthesis warnings

Good Afternoon,

I'm using the PCIe Hard IP avmm Gen2 x1 in my design. There are a clock generator, a reset generator, the Hard IP configured as endpoint and an on-chip memory. I created the synthesis files with Qsys. I have two questions regarding the Quartus compilation:

1) During the Analysis and synthesis, Quartus gives me warnings about the PIPE signals of the IP and about some submodules files created by qsys; anyway the Analysis and synthesis ends correctly.

How should I manage these warning?

2) During the Fitting. I have a critical warning, because there is not a transceiver reconfiguration controller. Is it really necessary to use it?

Thanks

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    For the transceiver reconfiguration controller, yes, it is mandatory to connect it to the Hard IP to allow offset cancellation performed for transceiver channels.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    As for the PIPE signals warnings, probably you can paste some here for further understanding.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thank you for your answer nic_@.

    These are the warnings.

    Synthesis:

    Warning (10034) Output port "testout" at altpcie_cv_hip_avmm_hwtcl.v(291) has no driver

    Warning (10034) Output port "txsynchd0" at altpcie_cv_hip_avmm_hwtcl.v(485) has no driver

    Warning (10034) Output port "currentcoeff0" at altpcie_cv_hip_avmm_hwtcl.v(493) has no driver

    Warning (10034) Output port "currentrxpreset0" at altpcie_cv_hip_avmm_hwtcl.v(501) has no driver

    Warning (10034) Output port "txdatavalid0" at altpcie_cv_hip_avmm_hwtcl.v(428) has no driver

    Warning (10034) Output port "txswing0" at altpcie_cv_hip_avmm_hwtcl.v(468) has no driver

    Warning (10034) Output port "txblkst0" at altpcie_cv_hip_avmm_hwtcl.v(477) has no driver

    Warning (10764) Verilog HDL warning at altpcie_av_hip_ast_hwtcl.v(1264) converting signed shift amount to unsigned

    Warning (10858) Verilog HDL warning at altpcie_av_hip_128bit_atom.v(1480): object rst_ctrl_rxanalogreset used but never assigned

    Warning (12011) Net is missing source, defaulting to GND

    Warning (12020) The extra bits will be ignored

    Warning (12010) The extra bits will be driven by GND

    Warning (12030) The extra bits will be left dangling without any fan-out logic

    Fit:

    Critical Warning (184043) Fitter was unable to find Transceiver Reconfiguration Controllers associated with the following 2 XCVR PHY IP component blocks
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi,

    On the critical warning, once you have the reconfiguration controller connected, it should go away. As for the warnings, can you check if all the top level ports of the HIP connected? If yes, I think you could just ignore them. I believe these ports are not used by your current configuration.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi tiny007,

    thank you for your answer.

    I fixed the critical warning on the reconfiguration controller, modifying the Qsys project by adding the reconfig controller and the pcie reconfig driver.

    The other warnings are on the PIPE ports, only used in simulation: on the "cyclone v pcie hip user guide" it is written that they can be left floating in the Quartus compilation.

    The remaining warnings affect signals in the synthesis submodules files created by Qsys.

    How should I deal with these warnings?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    For the remaining warnings, probably you could try to simulate your design or test on hardware to see if it works as expected. These warnings might be safe to ignore.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi tiny007,

    I have already simulated the design with ModelSim, and it runs as expected. I can't test it on hardware because I don't have the board available, but I guess it might be safe to ignore the warnings (even though I will write to an Altera FAE to know something more about it - I have the same warnings also when I compile the Altera PCIe example designs).
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If the Modelsim simulation is okay, the design should work in the hardware if there is no hardware related issue ie signal integrity. Yes, you are right. You can further clarify with Altera FAE or MySupport to be safe and also because the example design also shows similar warnings.