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Honored Contributor
Honored ContributorAltera PCIe Hard IP avmm for cyclone V quartus synthesis warnings
Good Afternoon, I'm using the PCIe Hard IP avmm Gen2 x1 in my design. There are a clock generator, a reset generator, the Hard IP configured as endpoint and an on-chip memory. I created the syn...
Altera_ForumHonored Contributor
Honored ContributorHi,
On the critical warning, once you have the reconfiguration controller connected, it should go away. As for the warnings, can you check if all the top level ports of the HIP connected? If yes, I think you could just ignore them. I believe these ports are not used by your current configuration.
