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Altera_Forum
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10 years ago

Altera PCIe Hard IP avmm for cyclone V quartus synthesis warnings

Good Afternoon, I'm using the PCIe Hard IP avmm Gen2 x1 in my design. There are a clock generator, a reset generator, the Hard IP configured as endpoint and an on-chip memory. I created the syn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If the Modelsim simulation is okay, the design should work in the hardware if there is no hardware related issue ie signal integrity. Yes, you are right. You can further clarify with Altera FAE or MySupport to be safe and also because the example design also shows similar warnings.