Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAltera PCIe Hard IP avmm for cyclone V quartus synthesis warnings
Good Afternoon, I'm using the PCIe Hard IP avmm Gen2 x1 in my design. There are a clock generator, a reset generator, the Hard IP configured as endpoint and an on-chip memory. I created the syn...
Altera_ForumHonored Contributor
Honored ContributorHi tiny007,
thank you for your answer. I fixed the critical warning on the reconfiguration controller, modifying the Qsys project by adding the reconfig controller and the pcie reconfig driver. The other warnings are on the PIPE ports, only used in simulation: on the "cyclone v pcie hip user guide" it is written that they can be left floating in the Quartus compilation. The remaining warnings affect signals in the synthesis submodules files created by Qsys. How should I deal with these warnings?
