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Honored Contributor
Honored ContributorAltera PCIe Hard IP avmm for cyclone V quartus synthesis warnings
Good Afternoon, I'm using the PCIe Hard IP avmm Gen2 x1 in my design. There are a clock generator, a reset generator, the Hard IP configured as endpoint and an on-chip memory. I created the syn...
Altera_ForumHonored Contributor
Honored ContributorHi tiny007,
I have already simulated the design with ModelSim, and it runs as expected. I can't test it on hardware because I don't have the board available, but I guess it might be safe to ignore the warnings (even though I will write to an Altera FAE to know something more about it - I have the same warnings also when I compile the Altera PCIe example designs).
