Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Altera PCIe Hard IP avmm for cyclone V quartus synthesis warnings

Good Afternoon, I'm using the PCIe Hard IP avmm Gen2 x1 in my design. There are a clock generator, a reset generator, the Hard IP configured as endpoint and an on-chip memory. I created the syn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi tiny007,

I have already simulated the design with ModelSim, and it runs as expected. I can't test it on hardware because I don't have the board available, but I guess it might be safe to ignore the warnings (even though I will write to an Altera FAE to know something more about it - I have the same warnings also when I compile the Altera PCIe example designs).