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Honored ContributorAltera PCIe Hard IP avmm for cyclone V quartus synthesis warnings
Good Afternoon, I'm using the PCIe Hard IP avmm Gen2 x1 in my design. There are a clock generator, a reset generator, the Hard IP configured as endpoint and an on-chip memory. I created the syn...
Altera_ForumHonored Contributor
Honored ContributorFor the transceiver reconfiguration controller, yes, it is mandatory to connect it to the Hard IP to allow offset cancellation performed for transceiver channels.
