Occasional ContributorAbout VHDL description
After converting A/D conversion data to 2's complement value, I created float (IEEE754 32bit) conversion, but it does not work well.
Float conversion, 2's complement conversion, and peripheral part alone work, but when everything is connected, it doesn't work well.
As far as I have checked here, it does not appear to be a problem in terms of RTL, but it is possible that there is an "inappropriate description in terms of VHDL syntax that is not extracted by the compiler".
Sorry to trouble you, but it would be helpful if you could teach us the following points.
1) If the conditional expression part of the if statement is enclosed in parentheses, Is it okay if there is no space between if,then and parentheses?
2) Is there any problem with the following description in the description of the case statement?
process(N_RST, AD_CLK)
begin
if (N_RST = '0') then
s_connect_sig_buf <= (others => '0');
elsif (AD_CLK'event and AD_CLK = '0') then
case s_sig_cnt(3 downto 0) is
when "0000" => s_connect_sig_buf(13 downto 0) <= AD_DATA_SIG;
when "0001" => s_connect_sig_buf(27 downto 14) <= AD_DATA_SIG;
when "0010" => s_connect_sig_buf(41 downto 28) <= AD_DATA_SIG;
when "0011" => s_connect_sig_buf(55 downto 42) <= AD_DATA_SIG;
when "0100" => s_connect_sig_buf(69 downto 56) <= AD_DATA_SIG;
when others => s_connect_sig_buf <= (others => '0');
end case;
end if;
end process;
3) There are places where TAB instead of space is used between the signal name and ":" in the Entity, signal statement.Is this a problem?
4) There is a place where TAB instead of space is used between the signal name and "<=" in the assignment statement.Is this a problem?
Any hints to solve the problem would be greatly appreciated.
Please note that the .vhd file itself is provided by another company and cannot be posted here.
