Occasional Contributor
ContributorHi @Yamada1 ,
It's unclear from your message what specifically you mean by " it does not work well".
But, short answers to your specific questions, in order of simplicity:
1) Yes, that's ok as far as VHDL is concerned. Whitespace around the parentheses is optional.
3) and 4) Not a problem as far as VHDL is concerned. It doesn't care about what type of whitespace characters you use.
2) The case statement itself looks ok, if the functionality is what you intended. But your code snippet contains an oddity, the use of a negative edge clock. Not something you'd want to do in general, unless you have a very good reason and a very good understanding of the issues involved in crossing between regions of logic using opposite edges of the clock. Is this possibly what's biting you when interfacing with other modules?... Also, you're using an asynchronous reset, which in most situations can and should be avoided, again, unless you have a good reason and good understanding of the issues involved.
And in general, I would encourage you to go gain at least some basic working proficiency in VHDL if you're going to be working with it. You can't learn VHDL from a message board. I recommend the books written by Peter Ashenden as a good starting point.
Cheers,
-Roee
Occasional ContributorThank you for pointing out the details.
"it does not work well" means that the 2's complement to floating point conversion part does not work as intended.
Also, the negative edge clock is used because the FIFO is connected after this, and the FIFO user guide states that the data transitions with the negative edge clock. (FIFO uses IP)
Asynchronous reset part inputs power-on reset signal It is the part that is not driven by other logic in the FPGA while the FPGA is running.
I understand that asynchronous resets should be avoided unless there is a specific reason to do so.
Thank you for your patience in answering even my elementary questions.
