Yamada1
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Re: About pin states from the end of MAX10 configuration to transition to user mode
Thank you for your answer. I apologize for not being clear enough. NurAiman_M_Intel told me that the I/O buffer during initialization will be TRISTATE/HIGH-IMPEDANCE/HIGH-Z regardless of the logic state. So, if the logic is Y=(A and B) or (C and D) and Y, A, B, C, and D are connected to INOUT pins, then I wanted to know what state A, B, C, and D will be at the time of initialization (0, 1, Hi-Z, the external state of the input pin is visible as is, etc.), which is the intention of question 2). I apologize for the trouble, but thank you in advance.1.5KViews0likes0CommentsRe: About pin states from the end of MAX10 configuration to transition to user mode
Thank you for your reply. I'm sorry to ask a second question, but I would appreciate it if you could explain the following points. 1) You said that the logic is initialized to '0', but does this mean that the final output will be '0' regardless of the configuration? If the logic Y=(A and B) or (C and D) is configured and this is initialized, does that mean that Y='0' will be the result if it is initialized regardless of the values of A to D? 2) You said that all I/O buffers are TRISTATE/HIGH-IMPEDANCE/HIGH-Z, but if the logic Y=(A and B) or (C and D) is initialized, what values will A to D have? I apologize for the trouble, but thank you in advance.1.5KViews0likes2CommentsAbout pin states from the end of MAX10 configuration to transition to user mode
According to the Intel® MAX® 10 FPGA Configuration User Guide, logic and registers are initialized and I/O buffers are enabled after configuration is complete. It would be helpful if you could teach me the following points. 1) Does this mean that the register is initialized to '0'? 2) Is it correct that logic initialization means finalizing the logic of the design? Also, if the logic input is connected to an I/O buffer, is it set to '0' or '1' at initialization? 3) If the understanding in 1) is incorrect, is it correct to understand that the register will have the initial value according to the design? (If it becomes '1' with a synchronous or asynchronous reset, that register becomes '1' with initialization, etc.) We apologize for the inconvenience and appreciate your understanding.1.6KViews0likes7CommentsRe: About MAX10 IO pin pull-up
Thank you for your comment. In the answer from AqidAyman_Intel, it was said that weak pull-up is disabled by default. Since it was a machine translation, there was a possibility of a mistranslation, so I checked to see if it was recognized. Also, I'm sorry for the lack of words. What I wanted to check in question 4) was whether the I/O pins are floating when the power is off, or whether they are connected to weak pull-ups. This is because the device connected to the I/O of the circuit under investigation starts up first, and I wanted to know the state of the MAX10's I/O pins when the power is turned off. We apologize for the inconvenience, but it would be helpful if you could teach us.2.5KViews0likes1CommentRe: About MAX10 IO pin pull-up
Thank you for answering. Thank you for explaining the details. Is it okay to understand the following? 1) Weak pull-up is disabled by default, but can be enabled through settings from the Quartus Prime software. 2) When weak pull-up is enabled, it prevents I/O pins from floating during power-up and power-down. 3) I/O pins are floating when the power is completely off. Also, I apologize for the repeated questions, but I would appreciate it if you could explain the following points. 4) If weak pull-up is enabled, are the I/O pins floating from power-on until POR operates? Or will the weak pull-up be enabled from the moment the power is turned on, and the power supply voltage will be visible during power-up? We apologize for the inconvenience and appreciate your understanding.2.6KViews0likes3CommentsAbout MAX10 IO pin pull-up
It would be helpful if you could tell me about the pull-up of the IO pin of MAX10. 1) In the UG-M10PWR, it is stated that the tri-state and weak pull-up resistors are enabled during power-up due to the POR circuit, but is this also the case during the power-down sequence? 2) If the power is completely turned off, will the weak pull-up resistor on the I/O pin not work? (In other words, will the I/O pin be floating?) We apologize for the inconvenience and appreciate your understanding.Solved2.7KViews0likes7CommentsAbout Max10 power connection
I was planning to use 10M02SCE144I7G and proceeded with reference to the Pin Connection Guidelines. was also using the circuit diagram of "EK-10M08E144" as a reference, but I noticed some differences with the guidelines. It would be helpful if you could teach me the following points. 1) According to the guidelines, the regulators for VCC_ONE and VCCIO are separate in any single supply configuration example. On the other hand, in the circuit diagram of "EK-10M08E144", although a 0.1Ω resistor is included, VCC_ONE and VCCIO are supplied from the same regulator. Is there any problem with the connection? 2) In the guidelines, "Share" is written in the Regulator Sharing column of VCC_ONE and VCCIO. There is no specific explanation, but is it okay to assume that VCC_ONE and VCCIO can be supplied from the same regulator as long as the voltage used is the same? We apologize for the inconvenience and appreciate your understanding.Solved1.3KViews0likes2CommentsRe: About loading constraints
Thank you for answering. I understand that if the -to nodes are the same, the previous description and when using wildcards will have the same behavior. In addition, there was a question about the purpose in the comment received at 1:02 AM on 3/18, but the purpose of setting a false path is to "exclude it from being analyzed by the timing analyzer." Thank you very much for your detailed explanation of the details.3.6KViews0likes0CommentsRe: About loading constraints
Thank you for answering. We have confirmed that this can be avoided by using a wildcard for the target as in the case of input ports. I tried it and realized that I was able to avoid this by changing line 17 of the SDC file as shown below, but is this correct? set_false_path -from [get_pins {s_rlo_clk_cnt|clk}] -to [get_ports {RLO_CLK_NODE}] We apologize for the inconvenience and appreciate your understanding.3.7KViews0likes0Comments