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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

About pin states from the end of MAX10 configuration to transition to user mode

According to the Intel® MAX® 10 FPGA Configuration User Guide, logic and registers are initialized and I/O buffers are enabled after configuration is complete. It would be helpful if you could teach ...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago
Hi,
when starting user mode, registers are initialized to 0 unless explicitly defined otherwise in your logic description.
Unregistered (combinational) signals are getting a logic level according to defined logic, this applies of course to unregistered outputs as well.
I don't understand your initial point 2. Inputs are getting the state driven to it externally. In case you are asking about non- tristated INOUT pins, they are reading back the state driving to it from the FPGA.
Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Thank you for your answer.
I apologize for not being clear enough.
NurAiman_M_Intel told me that the I/O buffer during initialization will be TRISTATE/HIGH-IMPEDANCE/HIGH-Z regardless of the logic state.
So, if the logic is Y=(A and B) or (C and D) and Y, A, B, C, and D are connected to INOUT pins, then I wanted to know what state A, B, C, and D will be at the time of initialization (0, 1, Hi-Z, the external state of the input pin is visible as is, etc.), which is the intention of question 2).
I apologize for the trouble, but thank you in advance.