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Honored Contributor
Honored Contributorabout time quest constraints
Hi to all.
I have a little question. I have cyclonevgt dev board. I have to connect a D/A converter to pins of fpga. I create a PLL clock out 100Mhz, routed at a pin of fpga. I create a 14 bit data bus, routed at pins of fpga. I have set timequest so that the data bus has 2ns setuptime and 2ns hold time, respect to the clock. what are the commands to use? Regards, Luca10 Replies
Altera_ForumHi,
there are two ways I could interpret your text:- the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC, or
- the clock is generated with a PLL outside the FPGA, and it is routed to an FPGA input pin as well as the DAC clock input
- Altera_Forum--- Quote Start --- Hi, there are two ways I could interpret your text:
- the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC, or
- the clock is generated with a PLL outside the FPGA, and it is routed to an FPGA input pin as well as the DAC clock input
- the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC.
- Altera_Forum--- Quote Start --- Hi GooGooCluster! In my case
- the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC.
- Altera_Forum--- Quote Start --- max output delay should be set to (+2ns) and min to (-2ns) assuming data and clock arrive at DAC with equal delay --- Quote End --- Thank you! Max and min delays are delays from data bus referenced to clock, right? I set it from timequest menu?
- Altera_Forum--- Quote Start --- Thank you! Max and min delays are delays from data bus referenced to clock, right? I set it from timequest menu? --- Quote End --- you put your constraints in sdc file(edit by hand or through timequest). reference clock should be output clock that goes to DAC (not input clock to PLL) so you need to declare the output clock.
- Altera_Forum--- Quote Start --- you put your constraints in sdc file(edit by hand or through timequest). reference clock should be output clock that goes to DAC (not input clock to PLL) so you need to declare the output clock. --- Quote End --- Can you write here the sdc command, for max and min delays? Regards, Luca
- Altera_Forum--- Quote Start --- Can you write here the sdc command, for max and min delays? Regards, Luca --- Quote End --- Come on Luca. Plenty examples around. set_output_delay -max 2 -clock dac_output_clock [get_ports DAC_Data*] set_output_delay -min -2 -clock dac_output_clock [get_ports DAC_Data*]
- Altera_Forum--- Quote Start --- Come on Luca. Plenty examples around. set_output_delay -max 2 -clock dac_output_clock [get_ports DAC_Data*] set_output_delay -min -2 -clock dac_output_clock [get_ports DAC_Data*] --- Quote End --- Thank you very much!
- Altera_Forum--- Quote Start --- Come on Luca. Plenty examples around. set_output_delay -max 2 -clock dac_output_clock [get_ports DAC_Data*] set_output_delay -min -2 -clock dac_output_clock [get_ports DAC_Data*] --- Quote End --- The external output clock pin (going to the dac) has name dac_clk, but does not appear in the clock list of timequest(get clocks). Must i declare the output pin of fpga as clock? how can I do?
- Altera_Forum--- Quote Start --- The external output clock pin (going to the dac) has name dac_clk, but does not appear in the clock list of timequest(get clocks). Must i declare the output pin of fpga as clock? how can I do? --- Quote End --- [create_generated_clock ...] and I don't remember syntax but there shoud be many examples around .
