about time quest constraints

Hi,

there are two ways I could interpret your text:

• the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC, or

• the clock is generated with a PLL outside the FPGA, and it is routed to an FPGA input pin as well as the DAC clock input

The timing constraints are different for both cases.

I suggest you to read a bit more about timing constraints, I recommend this https://www.altera.com/en_us/pdfs/literature/an/an433.pdf (https://www.altera.com/en_us/pdfs/literature/an/an433.pdf) and https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf).

Best regards,

GooGooCluster

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Hi,

there are two ways I could interpret your text:

• the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC, or

• the clock is generated with a PLL outside the FPGA, and it is routed to an FPGA input pin as well as the DAC clock input

The timing constraints are different for both cases.

I suggest you to read a bit more about timing constraints, I recommend this https://www.altera.com/en_us/pdfs/literature/an/an433.pdf and https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf.

Best regards,

GooGooCluster

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Hi GooGooCluster!

In my case

• the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC.

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Hi GooGooCluster!

In my case

• the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC.

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max output delay should be set to (+2ns) and min to (-2ns) assuming data and clock arrive at DAC with equal delay

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max output delay should be set to (+2ns) and min to (-2ns) assuming data and clock arrive at DAC with equal delay

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Thank you!

Max and min delays are delays from data bus referenced to clock, right?

I set it from timequest menu?

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Thank you!

Max and min delays are delays from data bus referenced to clock, right?

I set it from timequest menu?

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you put your constraints in sdc file(edit by hand or through timequest).

reference clock should be output clock that goes to DAC (not input clock to PLL) so you need to declare the output clock.

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you put your constraints in sdc file(edit by hand or through timequest).

reference clock should be output clock that goes to DAC (not input clock to PLL) so you need to declare the output clock.

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Can you write here the sdc command, for max and min delays?

Regards, Luca

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Can you write here the sdc command, for max and min delays?

Regards, Luca

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Come on Luca. Plenty examples around.

set_output_delay -max 2 -clock dac_output_clock [get_ports DAC_Data*]

set_output_delay -min -2 -clock dac_output_clock [get_ports DAC_Data*]

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Come on Luca. Plenty examples around.

set_output_delay -max 2 -clock dac_output_clock [get_ports DAC_Data*]

set_output_delay -min -2 -clock dac_output_clock [get_ports DAC_Data*]

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Thank you very much!

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Come on Luca. Plenty examples around.

set_output_delay -max 2 -clock dac_output_clock [get_ports DAC_Data*]

set_output_delay -min -2 -clock dac_output_clock [get_ports DAC_Data*]

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The external output clock pin (going to the dac) has name dac_clk, but does not appear in the clock list of timequest(get clocks).

Must i declare the output pin of fpga as clock?

how can I do?

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The external output clock pin (going to the dac) has name dac_clk, but does not appear in the clock list of timequest(get clocks).

Must i declare the output pin of fpga as clock?

how can I do?

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[create_generated_clock ...] and I don't remember syntax but there shoud be many examples around

.