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Altera_Forum's avatar
Altera_Forum
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9 years ago

about time quest constraints

Hi to all. I have a little question. I have cyclonevgt dev board. I have to connect a D/A converter to pins of fpga. I create a PLL clock out 100Mhz, routed at a pin of fpga. I create a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Can you write here the sdc command, for max and min delays?

Regards, Luca

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Come on Luca. Plenty examples around.

set_output_delay -max 2 -clock dac_output_clock [get_ports DAC_Data*]

set_output_delay -min -2 -clock dac_output_clock [get_ports DAC_Data*]