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Honored Contributor
Honored Contributorabout time quest constraints
Hi to all. I have a little question. I have cyclonevgt dev board. I have to connect a D/A converter to pins of fpga. I create a PLL clock out 100Mhz, routed at a pin of fpga. I create a...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- max output delay should be set to (+2ns) and min to (-2ns) assuming data and clock arrive at DAC with equal delay --- Quote End --- Thank you! Max and min delays are delays from data bus referenced to clock, right? I set it from timequest menu?
