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Hi,
there are two ways I could interpret your text:
- the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC, or
- the clock is generated with a PLL outside the FPGA, and it is routed to an FPGA input pin as well as the DAC clock input
The timing constraints are different for both cases.
I suggest you to read a bit more about timing constraints, I recommend this
https://www.altera.com/en_us/pdfs/literature/an/an433.pdf and
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf.
Best regards,
GooGooCluster
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Hi GooGooCluster!
In my case
- the clock is generated with a PLL inside the FPGA, and an FPGA output brings it to the DAC.
Honored Contributor
