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Altera_Forum's avatar
Altera_Forum
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9 years ago

about time quest constraints

Hi to all. I have a little question. I have cyclonevgt dev board. I have to connect a D/A converter to pins of fpga. I create a PLL clock out 100Mhz, routed at a pin of fpga. I create a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Thank you!

Max and min delays are delays from data bus referenced to clock, right?

I set it from timequest menu?

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you put your constraints in sdc file(edit by hand or through timequest).

reference clock should be output clock that goes to DAC (not input clock to PLL) so you need to declare the output clock.