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Altera_Forum's avatar
Altera_Forum
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16 years ago

about clock gating for multiple blocks

Hi :

I am now trying to implement clock gating to a large design.

There are 15 basic blocks which works almost in serial sequence. I planed to do the clock gating for them individually.

The global clock is out of a PLL and splitted into 15 clock gating unit and the output of each goes into each blocks.

The problem is these 15 sub-clocks must be synchronized and now there is some timing violation which seems that they are not.

I wonder if there is some constraints to do before synthesis or some smarter way in implenment the clock gating for this design

Thank you very much:) :) :)

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    no, I used the unit mentioned in the Altera datasheet, which contains a a latch (or a flipflop) and a and gate to implemented the clock gating.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Ah. That solution is not very good, timing wise.

    A better way to do it is either to use ATLCLKCTRL blocks to gate the clocks or to use clock enables instead of gated clocks.

    However, using ALTCLKCTRL only works if your device has enough clock networks.

    Since you have quite a few blocks, you'll most likely want to use clock enables (or a mix of gated clocks and clock enables).

    I recommend you take a look at this thread: http://www.alteraforum.com/forum/showthread.php?t=2388
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Hi :

    I am now trying to implement clock gating to a large design.

    There are 15 basic blocks which works almost in serial sequence. I planed to do the clock gating for them individually.

    The global clock is out of a PLL and splitted into 15 clock gating unit and the output of each goes into each blocks.

    The problem is these 15 sub-clocks must be synchronized and now there is some timing violation which seems that they are not.

    I wonder if there is some constraints to do before synthesis or some smarter way in implenment the clock gating for this design

    Thank you very much:) :) :)

    --- Quote End ---

    Hi,

    I also would recommend to use clock enable signals otherwise you will run into a lot of timing issues like Hold time violations.

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You could argue, that when using gated clocks (according to the Altera suggestion) throughout the design, all gated clocks have the same delay related to the master clock and should be capable of exchaniging data without timing issues.

    The problem is however, that a gated clock can't use global clock tree resources and involves increased skew. You didn't tell about the purpose of clock gating in your design. In my opinion, saving energy would be one of the meaningful few reasons for it. If the purpose is just pausing of selected entities, a clock enable as suggested by pletz should be the preferred method.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    First, thank you all very much for the replies.:):)

    The purpose I did it is indeed to reduce the power. And I have looked up the way of clock enabling from the white paper of Altera. The principle seems not similar as clock gating. It actually disables the data path when the block is doing nothing, right?? If it does so, will it save power as much as clock gating does??

    And, if I use the ATLCLKCTRL as clock gating, will the complier handle those clock routings in the correct way (considering the shews and so on)??
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    clock control blocks are there to put clock back on clock networks. It is up to you to cross domains safely. with so many domains you create, it is likely you will run in trouble. The benefit of power savings may be too trivial. You can have an idea about that in the power analyser. You can use dc fifos across domains

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    If it does so, will it save power as much as clock gating does??

    --- Quote End ---

    If I remember right, the power analyzer counts toggling registers rather than clocked registers. I guess, there should be a difference in power consumption between clocked and totally idle, but it's probably not very high. So I wonder, if the clock gating effort counts at all.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I know the power saving can be trivial. However, it is sort of my assignment to investigate the power reduction method of a FPGA design. And I cannot come up with other tricks much better than this clock gating. The design is not large actually but applied in a certain occasion which has strick require about power.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes I see. You should measure in a real hardware setup, if any power saving is achieved with clock gating versus clock enable. If it's still meaningful, all options of clock gating have been discussed. The preferred way is with clock control blocks, otherwise you have to an increased effort to achieve timing closure. If FIFOs would be required for synchronization, the power saving effect is most likely exhausted.