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Hi :
I am now trying to implement clock gating to a large design.
There are 15 basic blocks which works almost in serial sequence. I planed to do the clock gating for them individually.
The global clock is out of a PLL and splitted into 15 clock gating unit and the output of each goes into each blocks.
The problem is these 15 sub-clocks must be synchronized and now there is some timing violation which seems that they are not.
I wonder if there is some constraints to do before synthesis or some smarter way in implenment the clock gating for this design
Thank you very much:) :) :)
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Hi,
I also would recommend to use clock enable signals otherwise you will run into a lot of timing issues like Hold time violations.
Kind regards
GPK
Honored Contributor
