about clock gating for multiple blocks

First, thank you all very much for the replies.:):)

The purpose I did it is indeed to reduce the power. And I have looked up the way of clock enabling from the white paper of Altera. The principle seems not similar as clock gating. It actually disables the data path when the block is doing nothing, right?? If it does so, will it save power as much as clock gating does??

And, if I use the ATLCLKCTRL as clock gating, will the complier handle those clock routings in the correct way (considering the shews and so on)??