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Altera_Forum
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16 years ago

about clock gating for multiple blocks

Hi : I am now trying to implement clock gating to a large design. There are 15 basic blocks which works almost in serial sequence. I planed to do the clock gating for them individually. T...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I know the power saving can be trivial. However, it is sort of my assignment to investigate the power reduction method of a FPGA design. And I cannot come up with other tricks much better than this clock gating. The design is not large actually but applied in a certain occasion which has strick require about power.