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Altera_Forum
Honored Contributor
16 years agoYes I see. You should measure in a real hardware setup, if any power saving is achieved with clock gating versus clock enable. If it's still meaningful, all options of clock gating have been discussed. The preferred way is with clock control blocks, otherwise you have to an increased effort to achieve timing closure. If FIFOs would be required for synchronization, the power saving effect is most likely exhausted.