about chip planner in Quartus II

Thanks gee for response.

I take the picture of my test file:

1) bmp file: the chip planner design of the dely time

(http://mail.sso.ncku.edu.tw/cgi-bin/owmmbox/openwebmail-webdisk.pl/test.bmp?sessionid=l7697401*-session-0.819223314329101&currentdir=%2f&action=download&selitems=test.bmp)http://140.116.5.200/~e9493122/test.bmp (http://140.116.5.200/%7ee9493122/test.bmp)

2) jpg file: the waveform of the input/output signal in oscilloscope

(http://mail.sso.ncku.edu.tw/cgi-bin/owmmbox/openwebmail-webdisk.pl/wave.jpg?sessionid=l7697401*-session-0.819223314329101&currentdir=%2f&action=download&selitems=wave.jpg)http://140.116.5.200/~e9493122/wave.jpg (http://140.116.5.200/%7ee9493122/wave.jpg)

in this case, the fan-out connections are:

input port to the LE, which is the buffer: 2.074 ns

delay time in LE : 0.2 ns

LE to the output port : 0.612 ns

The estimate total delay time is around 3 ns, but the real total delay time is around 15 ns in scope.

You mean I should consider the input/output delay besides the delay time that are shown in chip planner.

I cannot find if the chip planner can show the input/output buffer delay as you mentioned.

Does it mean that the delay time shown on chip planner is totally not right, or I shoud add extra delay time of the input/output buffer by hand?

that is, 3 ns + (input/output delay which cannot be shown) = 15 ns

I am wondering that,

when the input/output delay is not correct, how can I trust the delay time shown in chip planner of other elements?

Thanks for your attention and help.

Hi ccmkn,

You can use the TimeQuest or Classic Timing Analyzer for more detailed timing analysis. They will give you accurate tpd including all components delay. Which are you using?

Regards,

Hi,

I didnt use the Timing analysis of TimeQuest or Classic timing analyzer.

Doesn't the timing analyzer just restrict the max time of the delay, not analysize the about delay time of my design in chip planner?

Maybe I confused you, sorry.

In my design, I have to make all elements, like buffers, have the same delay time, that is why I use chip planner to arrange the logicelements.

Its OK for me if the delay times are not short, as long as they are the same.

I will check if the Timing analysizer has other functions that I didnt know.

Thanks again

Hi,

The path delay you want to see may be shown in the Timing Anlayzer report. If it contains only logics and not FFs, you can find what you want in "tpd" report. Once you find the path under "tpd" report, right clik after seleting(left clicking) it and choose "list path.jpg". (shown in the tpd.jpg). Double click the path delay list which appears in the message window, it locates to the ChipPlanner. Now you can see what is shown in ChipPlanner and what is not.

Thanks,

Thanks gee very much.

I just followed the steps you replied.

There are surely some delay time in the input/output ports that are not shown in Chip planner.

That is a really help, thank you.

Though, the delay times in the report are still not match what I measured in scope.

If the report shown are the real delay times of my design, maybe it is wrong of my way to measure signals with the scope.

Hi, gee

According to your reply, I am wondering that why I cannot use the report when I have FFs?

Hi,

Yes, you can, but in the case you need to see tco report instead of tpd.

Regards!

--- Quote Start ---

Hi,

I didnt use the Timing analysis of TimeQuest or Classic timing analyzer.

Doesn't the timing analyzer just restrict the max time of the delay, not analysize the about delay time of my design in chip planner?

Maybe I confused you, sorry.

In my design, I have to make all elements, like buffers, have the same delay time, that is why I use chip planner to arrange the logicelements.

Its OK for me if the delay times are not short, as long as they are the same.

I will check if the Timing analysizer has other functions that I didnt know.

Thanks again

--- Quote End ---

Hi,

why do you need this constraint ? It will be very difficult to fulfill such requirement,

especially if you have to do it for a lot of elements.

Hi,

Thanks your attention, and sorry for my reply so late.

The reason why I must have the same delay time of elements is that

I am going to design the TDC(Time to Digital Convertor) by CPLD or FPGA.

The main goal is to design several stages that each one has the same delay time. After the pulse signal pass several stages and stop, say, n stages. I can have the pulse signal has time=n*(delay time of each stage).

There is a short and simple explaination.

If it is not worthy to change the placement by hand to achieve my goal.

Is there a more convenient way?

Thanks.