Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

about chip planner in Quartus II

I tried to change the placement and routing by Chip planner, and estimate the delay time. For example, I input a signal to a buffer and then output, the delay time in Chip planner is: after I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Does your estimation include input/output buffer delay? Also you need to consider the output delay depends on the output loading.