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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

about chip planner in Quartus II

I tried to change the placement and routing by Chip planner, and estimate the delay time. For example, I input a signal to a buffer and then output, the delay time in Chip planner is: after I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

The path delay you want to see may be shown in the Timing Anlayzer report. If it contains only logics and not FFs, you can find what you want in "tpd" report. Once you find the path under "tpd" report, right clik after seleting(left clicking) it and choose "list path.jpg". (shown in the tpd.jpg). Double click the path delay list which appears in the message window, it locates to the ChipPlanner. Now you can see what is shown in ChipPlanner and what is not.

Thanks,